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INTEGRATED CIRCUITS
DATA SHEET
SAA2013 Adaptive allocation and scaling for PASC coding in DCC systems
Preliminary specification File under Integrated Circuits, IC01 May 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
FEATURES * Wide operating voltage range: 2.7 to 5.5 V * Low power consumption: 13 mW; 3.0 V * Low power decode mode: 1 mW; 5.0 V * Sleep mode for low power and low Electromagnetic Interference (EMI) * Sophisticated allocation algorithm * Optimum sound quality * Three-wire L3 bus microcontroller interface * Stereo or 2-channel mono recording * Small surface mounted package (QFP; SOT307). ORDERING INFORMATION PACKAGE TYPE NUMBER PINS SAA2013H Note 44 PIN POSITION QFP(1) MATERIAL plastic GENERAL DESCRIPTION
SAA2013
The SAA2013 performs the adaptive allocation and scaling function in the Precision Adaptive Sub-band Coding (PASC) system. It is not required in playback only applications, and is only used during recording. To complete the PASC processor, a SAA2003 stereo filter and codec is required.
CODE SOT307-2
1. When using reflow soldering it is recommended that the Dry Packing instructions in the "Quality Reference Pocketbook" are followed. The pocketbook can be ordered using the code 9398 510 34011.
May 1994
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
BLOCK DIAGRAM
SAA2013
handbook, full pagewidth
VDD1 VDD2 14 24
VDD3 40
FS256 39
FRESET FDAI FDIR FSYNC 37 36 35 34
L3MODEM L3CLKM L3DATAM
3 4 5 MICROCONTROLLER BUS CONTROL AND SYNC COMPENSATION DELAY 32 31 30 26 23 33 FDCL FDWS SLEEP CLK24 RESET FDAO SFC BUS ALLOCATION AND SCALE FACTOR COMPUTATION
SAA2013
9 10 11
L3MODEC L3CLKC L3DATAC
6
25
44
20
21
22 RESOL1
MGB355
VSS1
VSS2
VSS3
NODONE RESOL0
Fig.1 Block diagram.
May 1994
3
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
PINNING SYMBOL TEST10 TEST11 L3MODEM L3CLKM L3DATAM VSS1 TEST12 TEST13 L3MODEC L3CLKC L3DATAC TEST1 TEST2 VDD1 TEST3 TEST4 TEST5 TEST6 TEST7 NODONE RESOL0 RESOL1 RESET VDD2 VSS2 CLK24 LOWPWR POR TEST8 SLEEP FDWS FDCL FDAO FDAI FSYNC FRESET FDIR TEST9 FS256 VDD3 May 1994 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 test input; connect to VSS test input; connect to VSS microcontroller interface mode input microcontroller interface clock input microcontroller interface data 3-state input/output supply ground test output; do not connect test output; do not connect codec interface mode output codec interface clock output codec interface data 3-state input/output test output; do not connect test output; do not connect supply voltage test mode input; connect to VDD test mode input; connect to VDD test input; connect to VSS test input; connect to VSS test input; connect to VSS nodone state selection input; connect to VDD resolution selection 0 input resolution selection 1 input reset input; active HIGH supply voltage supply ground 24.576 MHz clock input low power decode select input power on reset input test input; connect to VSS sleep mode select input filtered data word select filtered data clock filtered data output filtered data input sub-band synchronization on filtered reset signal input from SAA2003 filtered data direction input test input; connect to VSS system clock input; 256 x sample frequency (fs) supply voltage 4 I2S bus DESCRIPTION
SAA2013
TYPE I I I I I/O - O O O O I/O O O - I I I I I I I I I - - I I I I I I I O I I I I I I -
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
SYMBOL n.c. n.c. n.c. VSS3 PIN 41 42 43 44 not connected not connected not connected supply ground DESCRIPTION
SAA2013
TYPE - - - -
36 FRESET
35 FSYNC
38 TEST9
39 FS256
40 VDD3
44 VSS3
37 FDIR
43 n.c.
TEST10 TEST11 L3MODEM L3CLKM L3DATAM VSS1 TEST12 TEST13 L3MODEC
42 n.c.
41 n.c.
handbook, full pagewidth
34 FDAI
1 2 3 4 5 6 7 8 9
33 FDAO 32 FDCL 31 FDWS 30 SLEEP 29 TEST8
SAA2013
28 POR 27 LOWPWR 26 CLK24 25 VSS2 24 VDD2 23 RESET
L3CLKC 10 L3DATAC 11
NODONE 20
RESOL0 21
RESOL1 22
TEST1 12
TEST2 13
VDD1 14
TEST3 15
TEST4 16
TEST5 17
TEST6 18
TEST7 19
MGB356
Fig.2 Pin configuration.
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handbook, full pagewidth
May 1994
L analog output R baseband I 2S L analog input R ADC SAA7366 filtered I2 S ADAS3 SAA2013 ADAPTIVE ALLOCATION IEC958 DIGITAL AUDIO I/O TDA1315 search data analog CC L output analog CC R output SFC3 SAA2003 STEREO FILTER CODEC DAC TDA1305 sub-band 2 IS WRAMP TDA1381 WRITE AMP. FIXED HEAD RDAMP TDA1380 READ AMP. RAM 41464 BUFFER 64K x 4 speed control CAPSTAN DRIVE DRP SAA2023 OR SAA3323 DRIVE PROCESSOR TAPE
FUNCTIONAL DESCRIPTION
Philips Semiconductors
Adaptive allocation and scaling for PASC coding in DCC systems
6
AUDIO IN/OUT
MECHANICS DRIVERS
PASC PROCESSOR
TAPE DRIVE PROCESSING
detect switch
SYSTEM MICROCONTROLLER
Preliminary specification
SYSTEM CONTROL
MBD620
SAA2013
Fig.3 DCC system block diagram.
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
PASC processor The PASC processor is a dedicated Digital Signal Processor (DSP) engine which efficiently codes digital audio data at a bit rate of 384 kbits/s without affecting the sound quality. This is achieved using an efficient adaptive data notation and by only encoding the audio information which can be heard by the human ear. The audio data is split into 32 equal sub-bands during encoding. For each of the sub-bands a masking threshold is calculated. The samples from each of the sub-bands are included in the PASC data with an accuracy that is determined by the available bit-pool and by the difference between the signal power and the masking threshold for that sub-band. In decode, the sub-band signals are reconstructed into the full bandwidth audio signal. The stereo filter codec performs the splitting (encoding) and reconstruction (decoding), including the necessary formatting functions. During encoding, the adaptive allocation and scaling circuit calculates the required accuracy (bit allocation) and scale factors of the sub-band samples. Decode/encode control Selection of decode or encode is controlled using FRESET and FDIR. FRESET causes a general reset. The FDIR signal is sampled at the falling edge of the FRESET signal
SAA2013
to determine the operation mode. When FDIR is HIGH, SAA2013 is in decode mode. When FDIR is LOW the SAA2013 is in encode mode. See Fig.4. Reset When used with low-power mode disabled (LOWPWR = VSS), and with the SLEEP input LOW, SAA2013 is reset if the RESET pin is held HIGH for at least 5 periods of the CLK24 clock, see Fig.5. SAA2013 defaults to decode mode. When in low-power mode, the RESET pin is disabled. Sleep mode Sleep mode is entered by taking the SLEEP input HIGH with the LOWPWR pin connected to VSS; CLK24 and FS256 are stopped internally to the SAA2013, the 3-state buffers will have a high impedance, and outputs will freeze in the same state as just before the sleep mode became active (clocks stopped). To come out of sleep mode, the SLEEP input must be taken LOW again. To clear data present from before sleep was entered, this should be followed by a reset, see Fig.5.
handbook, full pagewidth
tH FRESET t su FDIR
MGB357
th
Fig.4 FDIR and FRESET timing.
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
SAA2013
handbook, full pagewidth
SLEEP
th RESET td CLK24
MGB358
Fig.5 SLEEP and RESET timing.
Low-power decode mode Low-power decode mode is made available by connecting the LOWPWR pin to VDD. With LOWPWR = VDD, low-power decode mode is entered 9 cycles of CLK24 after the SLEEP input is taken HIGH. In low-power decode mode, the L3 bus connections are connected straight trough the SAA2013, which is effectively bypassed. The compensation delay connection between pins FDAI and FDAO is no longer needed by the SAA2003, and CLK24 and FS256 are stopped internally to the SAA2013. To get out of low-power decode mode, it is necessary to take SLEEP LOW, FDIR LOW, and FRESET HIGH (in a normal application taking FDIR LOW and FRESET HIGH can be achieved by setting SAA2003 into encode mode), SAA2013 then performs an internal reset, and defaults to normal decode mode. The RESET pin does not reset the circuit from low-power decode mode. Power-On Reset (POR) When low-power decode mode is enabled (LOWPWR = VDD), a power-on reset circuit is required to ensure that the internal clocks are connected correctly at power-on. A suitable circuit is shown in Fig.6. This circuit will correctly reset the internal clock connection provided that the nominal value of the VDD supply is reached within 40 ms at power-on.
VDD
handbook, halfpage
1 F POR
VDD VSS
150 k
MGB359
VSS
Fig.6 POR circuit.
Encode mode In encode mode the SAA2013 receives sub-band filtered samples from SAA2003 on the FDAI pin. The SAA2013 has to collect a complete frame of sub-band data before the allocation and scale factor information can be calculated. So that the allocation and scale factor information is available in the same time frame as the audio samples at the output, the sub-band filtered samples are delayed by 480 FDWS periods. 1 One FDWS period is equal to --- where fs is the audio fs sample rate of 32, 44.1 or 48 kHz. The delayed samples are passed to the codec part of SAA2003 on the FDAO pin.
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
For each sub-band frame, SAA2013 calculates the allocation and scale factor index information required by the SAA2003. In order to synchronize the codec part of SAA2003, SAA2013 frequently requests status information from the codec. It monitors sample frequency, emphasis information and stereo mode, and uses the ready-to-receive bit of the codec to determine when to transfer information. Decode mode In decode the SAA2003 will transfer samples from FDAI to FDAO with a delay of 480 FDWS periods. Settings and status information can be sent to SAA2003 via SAA2013, but the SAA2013 does not itself act on this information. Transfer of this information is automatically synchronized to the ready-to-receive bit of SAA2003 by SAA2013. Filtered data interface The filtered data interface signals are given in Table 2. Table 2 Filtered data interface signals. INPUT/OUTPUT input input input output input FUNCTION filtered data interface word select filtered data interface bit clock filtered data input filtered data output filtered data sub-band synchronization Table 3 Order of samples. 0 L 0 1 2 . . 11 0 R 0 1 2 . . 11 1 L 0 1 2 . . 11 1 R 0 1 2 . . 11 2 L 0 1 2 . . 11 fs 64fs - - - Audio sample resolution section
SAA2013
The SAA2013 is designed for operation with audio input sources of 14, 15, 16 or 18-bit resolution. For optimum audio performance the bit allocation algorithm of the SAA2013 can be varied to suit the bit resolution of the audio source. This is done with the pins RESOL0 and RESOL1 as shown in Table 1. Table 1 Resolution set by pins RESOL0 and RESOL1. RESOL0 0 0 1 1 RESOL1 0 1 0 1
RESOLUTION 16 bits 18 bits 14 bits 15 bits
PIN FDWS FDCL FDAI FDAO FSYNC
FREQUENCY
The filtered data interface transfers sub-band filtered samples between the stereo filter codec SAA2003 and SAA2013. The interface is similar to a normal I2S interface, consisting of clock (FDCL), data (FDAI/FDAO) and word select lines (FDWS), except that the samples sent represent signals divided into 32 sub-bands. One frame of data consists of 12 samples from 32 sub-bands for both left and right channels, i.e.: 768 audio samples. Each audio sub-band sample is represented by a 24-bit two's complement number. The order in which the samples are sent is shown in Table 3. For two channel mono, the order is the same, but with Channel 1 samples in the place of left and Channel 2 samples in place of right.
SUB-BAND Channel Sample
2 R 0 1 2 . . 11
... ... ... ... ... ... ... ...
31 L 0 1 2 . . 11
31 R 0 1 2 . . 11
The signal FSYNC is used between each PASC frame to indicate the sending of samples for sub-band 0 (Fig.7).
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
SAA2013
handbook, full pagewidth
channel FDWS
32 bits left right
FDCL 1 bit 23 22 21 20 1 0 7 bit FSYNC timing L R L R
FDWS FSYNC sub-band
L
R
L
R
L
R
31
0 Tc t cH
1
31
0
t cL
FDCL t d4 t d3 FDAO t su1 FDAI FDWS t h1
MGB360
Fig.7 Filtered interface format.
Control interfaces Two 3-wire control interfaces are provided (referred to as `L3' interfaces). One is connected to the system microcontroller (L3MODEM, L3CLKM, L3DATAM where `M' represents microcontroller), the other to SAA2003 (L3MODEC, L3CLKC, L3DATAC where `C' represents codec). In general, control data is passed between SAA2003 and the microcontroller via SAA2013. This ensures that the microcontroller is buffered from the time-critical SAA2013 to SAA2003 interface during encode. The SAA2013 does not interpret the data from the microcontroller interface.
Status information from the codec is interpreted to ensure that SAA2013 quickly acts upon the status of SAA2003. The L3 bus operation is shown in Fig.8. There are three modes: 1. Address. 2. Data. 3. Halt. Each interface operates as either a master or a slave, where the master provides L3CLK and L3MODE. For the microcontroller to SAA2013 interface, the microcontroller is the master. For the SAA2013 to SAA2003 interface, SAA2013 is the master.
May 1994
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
SAA2013
handbook, full pagewidth
L3MODE
L3CLK
L3DATA
0
1
2
3
4
5
6
7
MGB361
Fig.8 L3 bus operation; address mode.
handbook, full pagewidth
L3MODE
L3CLK
L3DATA
0
1
2
3
4
5
6
7
MGB362
Fig.9 L3 single byte transfer.
handbook, full pagewidth
L3MODE
L3CLK
L3DATA
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
MGB363
Fig.10 L3 bus two byte transfer.
May 1994
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
ADDRESS MODE Address mode is entered by the master pulling L3MODE LOW. This causes the L3DATA line to act as an input on the slave, and 8 bits of address data are clocked into the slave. If the slave recognizes the address, it will set-up its internal state based on the 2 Least Significant Bits (LSBs) of the address. The slave than expects to send status data or receive control data. The addresses for SAA2013 are shown in Table 4. Table 4 MSB 0010 0010 0010 0010 SAA2013 addresses. LSB 0000 0001 0010 0011 L3 OPERATION MODE WDAT RDAT WCMD RSTAT FUNCTION extended settings allocation information settings status/peak read HALT MODE
SAA2013
Halt mode consists of pulling L3MODE LOW after sending data. It is used for marking the end of a data transfer mode which does not have an internal bit counter. SAA2013 interface modes The SAA2013 may be used to read and write from or to SAA2003. Information is transferred via a set of transit registers within SAA2013. DECODE OPERATION During decode, the SAA2013 does not perform allocation. Therefore no allocation and scale factor indices are sent to SAA2003. Settings and extended settings may still be sent to SAA2003, and SAA2013 monitors the status of the codec by reading status from it after every occurrence of FSYNC. Peak level data can also be transferred from SAA2003. ENCODE OPERATION In encode, the same information may be sent as for decode, and in addition, allocation/scale factor indices are sent to the codec by SAA2013. The interface modes are shown in Table 5.
The interface may be reset by sending an address of all zeros (`00000000'). This may be used to allow inter-operation with other devices sharing the L3CLK and L3DATA lines (e.g. SAA7345 CD decoder). DATA MODE In data mode, bytes of data are clocked into (e.g. control) or out of (e.g. status) the slave. A single byte transfer is shown in Fig.9. A two byte transfer is shown in Fig.10, between bytes there must be a pause during which the clock remains HIGH.
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
Table 5 MODE BIT 1 Decode 0 0 1 1 Encode 0 0 1 1 PRIORITY Each type of transfer has a priority. The priorities are: 1. Allocation/scale/settings (highest priority). 2. Status read. 3. Peak read. 4. Extended settings (lowest priority). ALLOCATION AND SCALE FACTOR TRANSFER The allocation and scale factor information sent from SAA2013 to SAA2003 during encode has the highest priority. The other types of transfer interleaved with the allocation/scale information. SETTINGS TRANSFER This is a 16-bit transfer. The microcontroller sends settings to SAA2003. SAA2013 only transfers these without taking notice of the contents. In encode, the settings are held in Table 6 Status bits. NAME bit rate index sample frequency indication RTRS (settings) RTRE (external settings) MODE SYNC CLKOK Tr0 and Tr1 EMPHASIS FUNCTION bit rate indication 44.1, 48, 32 kHz indication 1 = ready; 0 = not ready 1 = ready; 0 = not ready sub-band signal mode identification synchronization indication 1 = OK; 0 = not OK transparent bits emphasis indication BIT 0 0 1 0 1 0 1 0 1 extended settings - settings status/peak extended settings allocation/scale settings status/peak 8 - 16 16 or 48 8 48 x 16 16 16 or 48 Interface modes. ADDRESS INTERFACE MODE LENGTH (BITS)
SAA2013
DIRECTION microcontroller to SAA2003 - microcontroller to SAA2003 SAA2003 to microcontroller microcontroller to SAA2003 SAA2013 to SAA2003 microcontroller to SAA2003 SAA2003 to microcontroller
the transit registers, and sent next time that allocation is being sent. In decode, settings are sent as soon as possible subject to the RTRC flag from SAA2003. Before sending settings the microcontroller should read the status of SAA2013 to examine the Ready-To-Receive bit Settings (RTRS). After the settings have been received by SAA2013, RTRS will be made logic 0, until the settings have been sent to SAA2003. Only after RTRS is logic 1 again may the microcontroller send new settings. STATUS READ Status and peak information may be read from SAA2003 by the microcontroller. The status bits are defined in Table 6.
BIT B15 to B12 B11 and B10 B9 B8 B7 and B6 B5 B4 B3 and B2 B1 and B0
VALID IN encode/decode encode/decode encode/decode encode/decode encode/decode encode/decode encode/decode encode/decode encode/decode
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
Since the two bytes of status information are sampled separately, the bytes may result from different sub-band frames. The only valid bit rate code for the SAA2013 is 1100. The sample frequency indication is shown in Table 7. Table 7 Sample frequency indication. BIT 10 0 1 0 1 SAMPLE FREQUENCY 44.1 kHz; default 48.0 kHz 32.0 kHz do not use
SAA2013
is possible that peak data may contain an additional delay of 1 column (667 s minimum at 48 kHz, 1 ms maximum at 32 kHz). If the microcontroller attempts to read peak level data with a delay of less than 1 column, the peak level data from the previous reading will be repeated. Normally the microcontroller should allow at least 1 ms between reads. There is also a delay required between peak data words (Fig.13). If the SAA2013 does not have peak data available (for instance the microcontroller attempts two reads in very quick succession), it will return all peak data bits set to logic 0. The microcontroller can detect if valid peak data has been returned by inspecting bits T16 and T32. If both bits are set to logic 0 the data is not valid.
BIT 11 0 0 1 1
Ready-to-receive S or E indicates whether the SAA2013 is ready-to-receive new settings or extended settings from the microcontroller. This should be checked before sending new information. For details of the MODE, SYNC, CLKOK and transparent bits, refer to the "SAA2003 data sheet". The emphasis indication can be used to apply the correct de-emphasis. In encode SAA2013 will correct the calculated allocation if 5015 s emphasis is applied. When "CCITT J.17" emphasis is applied, the bit allocation remains the same as when no emphasis is applied. The 2 bytes of the status are `sampled' at different moments. So the information may not result from the same sub-band frame. When making repeated status reads (for instance reading the RTRS/RTRE flags before sending settings or extended settings), the microcontroller must send an address before each status read, to ensure that the byte counter in the interface is reset to logic 0. If this is not done, then the peak data will be read. Conversely, it is important not to send a new address after a status read if the peak data is required. PEAK READ Peak information is read by clocking a further 4 bytes of data after a status read. The data format is shown in Figs 11 and 12. Bits B17 to B31 contain a 15-bit unsigned peak, LSB first, channel indicated by bit B16. Bits B33 to B47 contain a 15-bit unsigned peak, channel indicated by bit B32. The peak data is delayed by 1 read period. If for example the microcontroller reads peak level data every 50 ms, the peak data sourced by SAA2013 will be 50 ms old. Also it May 1994 14
MSB
handbook, halfpage
LSB
00100011 STATUS MSB PEAK BYTE 1 PEAK BYTE 3 STATUS LSB PEAK BYTE 0 PEAK BYTE 2
MGB364
Fig.11 Peak level read format; SAA2013 to microcontroller.
MSB
handbook, halfpage
16 15-bit peak channel indicator bits 17 to 31
32 15-bit peak channel indicator bits 33 to 47
MGB365
Fig.12 Peak level format.
MSB
LSB
LSB
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
SAA2013
handbook, full pagewidth
15.625 s HALT STATUS BYTES PEAK 1 PEAK 2
MGB366
L3MODEC
Fig.13 Peak data timing.
EXTENDED SETTINGS This is a single byte transfer, valid during decode and encode. The sequence of operations is: 1. Microcontroller reads status from SAA2013, waiting for the flag RTRE to be set. 2. When RTRE is logic 1, the microcontroller writes address bit 0 is logic 0, bit 1 is logic 0. 3. One byte of extended settings is clocked into the transit register (SAA2013). 4. When it is possible (i.e. subject to RTRC being HIGH, and assuming that allocation or status is not waiting), the byte is transferred from the transit register to the SAA2003.
handbook, full pagewidth
L3MODEC t cH t cL t h2
t d1 L3CLKC t d3
t d2 L3DATAC (ADAS-SFC)
t d4 t h1
t d5
MGB367
Fig.14 L3 interface timing; SAA2013 to SAA2003 (address mode).
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
SAA2013
handbook, full pagewidth
L3MODEC
t d1 L3CLKC t su1 L3DATAC SFC-ADAS) t d3 t d2 L3DATAC (ADAS-SFC)
t cH
t cL
t h2
t h1
t d4 t h3
t d5
MGB368
Fig.15 L3 interface timing; SAA2013 to SAA2003 (data mode).
handbook, full pagewidth
L3MODEM
t d1 L3CLKM t su1 L3DATAM (microcontrollerADAS)
t cH
t cL
t h2
t h1
MGB369
Fig.16 L3 interface timing; microcontroller to SAA2013 (address mode).
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
SAA2013
handbook, full pagewidth
L3MODEM
t d1 L3CLKCM t su1 L3DATAM (microcontrollerADAS) t d3 t d2 L3DATAM (ADASmicrocontroller)
t cH
t cL
t h2
t h1
t d4 t h3
t d5
MGB370
Fig.17 L3 interface timing; microcontroller to SAA2013 (data mode).
handbook, full pagewidth
tL
L3MODEM/ L3MODEC t h2 L3CLKM/ L3CLKC t d5 L3DATA/ L3DATAC (OUTPUT)
MGB371
t d1
t d2
Fig.18 L3 interface timing; microcontroller to SAA2013 and SAA2013 to SAA2003 (halt mode).
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
SAA2013
handbook, full pagewidth
Tc24 t cL CLK24
MGB372
tcH
tf
tr
Fig.19 Input timing CLK24.
handbook, full pagewidth
CLK24
t su DATA
th
MGB373
t r, t f
Fig.20 Input signal timing for FSYNC, FRESET, FDIR, FDWS, L3MODEM, L3CLKM, L3DATAM and L3DATAC.
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
SAA2013
handbook, full pagewidth
FS256 td th FDAO
MGB374
Fig.21 Output signal timing FDAO.
handbook, full pagewidth
Tc t cL FDCL t d4 t d3 FDAO (FDAI) t su1 FDAI, FDWS
MGB375
t cH
t h1
Fig.22 Filtered data interface timing.
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
Current consumption The typical current consumption is shown in Fig.23.
SAA2013
MBD697
handbook, halfpage
10
I DD (mA) 8
6
4
2
0 2 3 4 5 VDD (V) 6
Tamb = 25 C.
Fig.23 Typical current consumption.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI II VO IO Tstg Tamb Ves PARAMETER supply voltage input voltage input current output voltage output current storage temperature operating ambient temperature electrostatic handling Human Body Model (HBM) Machine Model (MM) Notes 1. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 2. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. note 1 note 2 -2000 -200 +2000 +200 V V CONDITIONS MIN. -0.5 -0.5 - -0.5 - -65 -40 MAX. +6.5 VDD + 0.5 20 +6.5 20 +150 +85 V V mA V mA C C UNIT
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
SAA2013
CHARACTERISTICS VDD = 2.7 to 5.5 V; VSS = 0 V;Tamb = -40 to 85 C; unless otherwise specified; IOL and IOH derated by 75% for VDD < 4.5 V. SYMBOL Supply VDD IDD Istb Inputs VIL VIH ILI CI Outputs VOL VOH CL VIL VIH ILI CI VOL VOH CL fi tr tf tcH tcL fi LOW level output voltage HIGH level output voltage load capacitance IOL = 4 mA IOH = -4 mA 0 VDD - 0.4 - - - - - - - - - - - 0.4 VDD 30 V V pF LOW level input voltage HIGH level input voltage input leakage current input capacitance VI = 0 to VDD 0 0.7VDD -10 - - - - - 0.3VDD VDD +10 10 V V A pF supply voltage supply current standby current VDD = 3.0 V VDD = 5.0 V VDD = 5.0 V 2.7 4 7 - 5.0 5 10 - 5.5 6 12 400 V mA mA A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Inputs/outputs LOW level input voltage HIGH level input voltage 3-state leakage current input capacitance LOW level output voltage HIGH level output voltage load capacitance IOL = 4 mA IOH = -4 mA VI = 0 to VDD 0 0.7VDD -10 - 0 VDD - 0.4 - - - - 10 10 - - - - - 35 35 0.3VDD VDD +10 10 0.4 VDD 30 - 7 7 - - - - - 7 7 - - V V A pF V V pF
Clock input CLK24 input frequency rise time fall time HIGH time LOW time see Fig.19 24.576 - - - - MHz ns ns ns ns
Clock input FS256 input frequency fs = 48 kHz fs = 44.1 kHz fs = 32 kHz tr tf tcH tcL rise time fall time HIGH time LOW time 12.288 11.2896 8.192 - - - - MHz MHz MHz ns ns ns ns
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA2013
MAX.
UNIT
Inputs FSYNC, FRESET, FDIR, FDWS, L3MODEM, L3CLKM, L3DATAM and L3DATAC; referenced to CLK24 rising edge; see Fig.20; SLEEP = RESET = POR = logic 0 tsu th tr tf set-up time hold time rise time fall time 15 20 - - - - - - - - 200 200 ns ns ns ns
Inputs FDAI, FDCL, FDWS, FRESET and FDIR; referenced to FS256 rising edge; SLEEP = RESET = POR = logic 0 tsu th tr tf th td td3 td4 set-up time hold time rise time fall time 15 20 - - - - - - - - - - - - 200 200 - 30 - ns ns ns ns
Output FDAO; referenced to FS256 rising edge; see Fig.21; SLEEP = RESET = POR = logic 0 hold time delay time output delay time after FDCL HIGH output delay time after FDCL HIGH CL = 7.5 pF CL = 30 pF see Fig.22 see Fig.22 0 - 2Tc256 - 10(1) - ns ns ns
3Tc256 + 60(1) ns
Input FDCL; see Fig.22 Tc tcH tcL tsu1 th1 tH tsu th FDCL period FDCL HIGH time FDCL LOW time 280 Tc256 + 35(1) Tc256 + 35(1) 4Tc256(1) - - - - - - - - - - ns ns ns
Inputs FDAI and FDWS; see Fig.22 set-up time before FDCL HIGH hold time after FDCL HIGH 3Tc256 + 60(1) - Tc256 + 20(1) 1280 0 9Tc24(2) - - 210 370 ns ns
Input FRESET; see Fig.4 FRESET HIGH time FDIR set-up time before FRESET LOW FDIR hold time after FRESET LOW ns ns ns
SLEEP and RESET timing; see Fig.5; LOWPWR = logic 1 th td RESET hold time after SLEEP LOW CLK24 disable after SLEEP HIGH 5Tc24(2) 9Tc24(2) 210 370 - - ns ns
May 1994
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Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA2013
MAX.
UNIT
L3 interface timing; microcontroller to SAA2013 ADDRESS MODE; SEE FIG.16 td1 tcH tcL tsu1 th1 th2 L3MODEM LOW to L3CLKM LOW L3CLKM HIGH time L3CLKM LOW time L3DATAM input set-up time before L3CLKM HIGH L3DATAM input hold time after L3CLKM HIGH L3CLKM HIGH before L3MODEM HIGH 190 250 250 190 30 190 - - - - - - - - - - - - ns ns ns ns ns ns
DATA MODE; SEE FIG.17 td1 tcH tcL tsu1 th1 th2 td3 th3 td4 L3MODEM HIGH to L3CLKM LOW delay time L3CLKM HIGH time L3CLKM LOW time L3DATAM input set-up time before L3CLKM HIGH L3DATAM input hold time after L3CLKM HIGH L3CLKM HIGH before L3MODEM LOW L3MODEM HIGH to L3DATAM output valid L3DATAM output hold time after L3CLKM HIGH L3CLKM HIGH to L3DATAM output valid delay time between bits 7 and 8; no halt mode used 190 250 250 190 30 190 - 120 - - - - - - - - - - - - - - - - - - 380 - 360 530 ns ns ns ns ns ns ns ns ns ns
td2 td5
L3MODEM HIGH to L3DATAM output enabled delay time L3MODEM LOW to L3DATAM output disabled delay time
0 0
- -
50 50
ns ns
May 1994
23
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
SYMBOL PARAMETER CONDITIONS MIN. - - - - - TYP. - - - 50 50
SAA2013
MAX.
UNIT
HALT MODE; SEE FIG.18 tL td1 th2 td2 td5 L3MODEM LOW time L3MODEM HIGH to L3CLKM HIGH delay time L3CLKM HIGH before L3MODEM LOW L3MODEM HIGH to L3DATAM output enabled delay time L3MODEM LOW to L3DATAM output disabled delay time 190 190 190 0 0 ns ns ns ns ns
L3 interface timing; SAA2013 to SAA2003 ADDRESS MODE; SEE FIG.14 td1 tcH tcL th2 td3 th1 td4 td2 td5 L3MODEC LOW to L3CLKC LOW delay time L3CLKC HIGH time L3CLKC LOW time L3CLKC HIGH time before L3MODEC HIGH L3MODEC LOW to L3DATAC output valid delay time L3DATAC output hold time after L3CLKC HIGH L3CLKC HIGH to L3DATAC output valid delay time L3MODEC LOW to L3DATAC output enabled delay time L3MODEC HIGH to L3DATAC output disabled delay time 190 210 210 190 - 120 - 0 0 - - - - - - - - - - - - - 380 - 360 50 50 ns ns ns ns ns ns ns ns ns
May 1994
24
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - - - - TYP. - - - - - - 380 - 360 530
SAA2013
MAX.
UNIT
DATA MODE; SEE FIG.15 td1 tcH tcL tsu1 th1 th2 td3 th3 td4 L3MODEC HIGH to L3CLKC LOW L3CLKC HIGH time L3CLKC LOW time L3DATAC input set-up time before L3CLKC HIGH L3DATAC input hold time after L3CLKC HIGH L3CLKC HIGH time before L3MODEC LOW L3MODEC HIGH to L3DATAC output valid L3DATAC output hold time after L3CLKC HIGH L3CLKC HIGH to L3DATAC output valid between bits 7 and 8; no halt mode used 190 210 210 100 30 190 - 120 - - ns ns ns ns ns ns ns ns ns ns
HALT MODE; SEE FIG.18 tL td1 th2 L3MODEC LOW time L3MODEC HIGH to L3CLKC HIGH delay time L3CLKC HIGH time before L3MODEC LOW 190 190 190 - - - - - - ns ns ns
L3 interface delays in bypassed mode; LOWPWR = logic 1 tpd1 propagation delay from L3MODEM to L3MODEC; L3DATAM to L3DATAC; L3CLKM to L3CLKC propagation delay from L3DATAM to L3DATAC; L3CLKM to L3CLKC propagation delay from L3DATAM to L3DATAC; L3MODEM to L3MODEC - - 35 ns
tpd2
-20
-
+4
ns
tpd3
-20
-
+4
ns
Notes 1. Tc256 is a clock period of FS256. 2. Tc24 is a clock period of CLK24.
May 1994
25
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
PACKAGE OUTLINE
SAA2013
handbook, full pagewidth
seating plane
0.1 S
S
12.9 12.3 44 1 34 33 1.2 (4x) 0.8 B
pin 1 index 0.8
11 12 0.40 0.20 10.1 9.9 22
23
0.40 0.20
0.15 M A
1.2 (4x) 0.8
0.15 M B
10.1 9.9
12.9 12.3
X
0.8
A
0.85 0.75 1.85 1.65 0.25 0.05 0.25 0.14 2.10 1.70
MBB944 - 2
detail X
0.95 0.55
0 to 10 o
Dimensions in mm.
Fig.24 Plastic quad flat-pack, 44-pin (short) (QFP44SL).
May 1994
26
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
SOLDERING Plastic quad flat-packs BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be
SAA2013
applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
May 1994
27
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA2013
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N.V.
May 1994
28
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
NOTES
SAA2013
May 1994
29
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
NOTES
SAA2013
May 1994
30
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC coding in DCC systems
NOTES
SAA2013
May 1994
31
Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2327, Fax. (011)829-1849 Canada: INTEGRATED CIRCUITS: Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 601 Milner Ave, SCARBOROUGH, ONTARIO, M1B 1M8, Tel. (0416)292 5161 ext. 2336, Fax. (0416)292 4477 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0-50261, Fax. (9)0-520971 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: PHILIPS COMPONENTS UB der Philips G.m.b.H., P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: PHILIPS HONG KONG Ltd., Components Div., 6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)428 6729 India: Philips INDIA Ltd, Components Dept, Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)640 000, Fax. (01)640 200 Italy: PHILIPS COMPONENTS S.r.l., Viale F. Testi, 327, 20162 MILANO, Tel. (02)6752.3302, Fax. (02)6752 3300. Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5028, Fax. (03)3740 0580 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: Philips Components, 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB Tel. (040)783749, Fax. (040)788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546. Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)14163160/4163333, Fax. (01)14163174/4163366. Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., Components Division, 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382. Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319. Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors Limited, P.O. Box 65, Philips House, Torrington Place, LONDON, WC1E 7HD, Tel. (071)436 41 44, Fax. (071)323 03 42 United States: INTEGRATED CIRCUITS: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd., P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404, Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BAF-1, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD31 (c) Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
513061/1500/01/pp32 Document order number: Date of release: May 1994 9397 731 90011
Philips Semiconductors

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